Peer-to-peer communication environments such as local area networks (LANs) have lately become the technique of choice for interconnecting different types of computer equipment, primarily because of their minimal expense and ease of use.
In a network using the well-known Ethernet signaling technique, the network devices, such as stations, repeaters, bridges, and the like, must include a circuit for receiving and decoding an incoming Ethernet signal. Ethernet signals are self-clocking, Manchester-encoded signals having a finite packet length. Such signals are self-clocking in the sense that they contain both data and clock information, thereby eliminating the need to transmit a separate clock signal. This is accomplished by insuring that a level transition, from zero to one or one to zero, occurs in the middle of every transmitted bit. The time duration of an Ethernet signal is limited by the maximum packet length of 1518 bytes.
Certain known techniques are especially adapted for detecting self-clocking signals. For example, U.S. Pat. No. 4,745,626, issued to Wells, describes a Manchester-encoded signal receiver in which transitions in an incoming signal are detected and then clocked into a shift register. The shift register is clocked by a local clock signal having a frequency which is a multiple of the fundamental data rate of the incoming signal. A logic circuit connected to the shift register determines when phase shifts in the incoming signal occur, so that the incoming data may be decoded without the need for a feedback circuit such as a phase locked loop.
Unfortunately, the lack of feedback in such a circuit means that when the incoming signal drifts more than a slight amount from the local clock, synchronization is easily lost.
Another technique is disclosed in U.S. Pat. No. 4,450,572, issued to Stewart et al., and assigned to Digital Equipment Corporation, the assignee of this application. In Stewart, et al. circuit, a flip-flop, exclusive-OR gate, and delay line separate the data and clock signals. The data signal is fed to a serial shift register clocked by the clock signal; an internal synchronizing circuit re-synchronizes the output of the shift register to an independent clock source.
While this technique works well for its intended purpose, it does have certain shortcomings. In particular, it is asynchronous, in the sense that certain components switch in phase with the clock signal embedded in the incoming signal, and certain other components switch in phase with a local reference signal having a phase and/or frequency which differs from the embedded clock signal. In other words, a first clock signal is extracted from the Manchester-encoded incoming signal, and then use the first clock signal to sample the incoming signal to recover the input data. Once the data is recovered, the input data is re-timed by sampling it again with a second clock signal, which is a locally generated signal asynchronous to the first clock signal.
The greater the number of asynchronous clock signals in a circuit, the more complicated and expensive it becomes. A particularly vexatious problem in such a circuit is to resolve metastable conditions, which may occur when a flip-flop is clocked before its input signals reach a stable state. This condition is more likely to occur in a circuit where input signals to a flip-flop may change asynchronous to the clock signal driving the flip-flop.
Thus, it would be desirable to minimize the number of asynchronous clock signals in circuits such as an Ethernet signal decoder. In fact, it is preferable for all components of such a circuit to operate in phase with a single local oscillator, which would then minimize the cost and complexity of such a device, while improving its reliability.